Design and Simulation of an Optimized QCA-Based Half Adder Using Bistable Quantum Cells

Abstract

Quantum-dot Cellular Automata (QCA) is an emerging nanotechnology that offers a potential alternative to conventional CMOS-based digital logic by enabling ultra-dense, low-power computational architectures. This paper presents the design and simulation of a novel half adder using QCA technology, employing bistable quantum cells to enhance circuit efficiency and reduce area and latency. The proposed design aims to improve upon traditional logic gate implementations by minimizing complexity while maintaining functional accuracy. Simulations are conducted using QCA Designer to validate the structure's performance in terms of area, cell count, and delay. The results confirm the feasibility of the design for next-generation nanoelectronic applications in arithmetic logic circuits.